1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device incorporated in an analog circuit and used for generation of a reference voltage.
2. Description of the Background Art
As the trend toward multimedia information grows stronger, there is an increasing demand for a system for processing analog signals, such as audio and video signals, at high speeds and with high precision. A hybrid analog-digital LSI circuit which contains a MPU (Micro Controller Unit), a DSP (Digital Signal Processor), and D-A and A-D converters on a single semiconductor chip can achieve lower power consumption in addition to higher-speed and higher-precision operation, and is the mainstream of LSI development.
A digital circuit part of the hybrid analog-digital LSI circuit has been increased in the degree of integration with the progression of a MOS circuit micromachining technique, and has achieved the high-speed operation, high performance and low power consumption. However, the D-A and A-D converters of the hybrid analog-digital LSI circuit which are essential for system input and output have not yet achieved so high a degree of integration and so low power consumption as the digital circuit part under the constrains of machining precision and physical characteristics of transistors under present circumstances.
In recent years, products with the hybrid analog-digital LSI circuit incorporated in transportable equipment have been coming along. However, since the LSI circuit for incorporation in transportable equipment is assumed to be battery-operated, the reduction in power consumption of such an LSI circuit is the highest-priority technical object to be accomplished.
An example of high-speed, high-precision and low-power-consumption D-A converters manufactured using the CMOS process includes a current cell matrix type D-A converter. FIG. 11 is a block diagram showing the general construction of the current cell matrix type D-A converter.
As illustrated in FIG. 11, the current cell matrix type D-A converter comprises a cell matrix MX including a plurality of current source cells SL arranged in a matrix form, an X-decoder XD for specifying the row position of the cell matrix MX, a Y-decoder for specifying the column position of the cell matrix MX, and a reference voltage generator circuit RG for providing an operating voltage to the current source cells SL.
The X-decoder XD receives four bits b3, b2, b1 and b0 of input digital code, and the Y-decoder YD receives four bits b7, b6, b5 and b4 of input digital code. The number of current source cells SL to be turned on is established based on a total of eight bits of input digital code.
Each of the current source cells SL has two outputs I.sub.OUT and I.sub.OUTB, the output I.sub.OUT being grounded through a resistor R.sub.L, the output I.sub.OUTB being grounded through a resistor R.sub.LB.
FIG. 12 shows the construction of a current source cell SL. The current source cell SL of FIG. 12 comprises an input section including an AND gate G1 having two inverting inputs and an OR gate G2 having two inputs one of which is connected to the output of the AND gate G1; P-channel MOS transistors (referred to hereinafter as PMOS transistors) M1, M2, M3, M4; and N-channel MOS transistors (referred to hereinafter as NMOS transistors) M5, M6.
In the input section, the two inputs of the AND gate G1 receive an output from the X-decoder XD and an output from the Y-decoder YD respectively, and the inverting input of the OR gate G2 receives another output from the Y-decoder YD.
Regarding the construction of the current source cell, the sources of the PMOS transistors M3 and M4 are connected to a power supply V.sub.DD, and the drains of the PMOS transistors M3 and M4 are connected to the sources of the PMOS transistors M1 and M2, respectively. The drains of the PMOS transistors M1 and M2 provide respectively the outputs I.sub.OUTB and I.sub.OUT complementary to each other.
The drain of the PMOS transistor M3 is connected to the drain of the NMOS transistor M5, and the drain of the PMOS transistor M4 is connected to the drain of the NMOS transistor M6. The sources of the NMOS transistors M5 and M6 are grounded. The gate of the NMOS transistor M5 is connected to the drain of the NMOS transistor M6, and the gate of the NMOS transistor M6 is connected to the drain of the NMOS transistor M5.
A reference voltage V.sub.BIAS from the reference voltage generator circuit RG is applied to the gates of the PMOS transistors M1 and M2.
The output from the OR gate G2 is applied to the gate of the PMOS transistor M3 and is also inverted by an inverter G3. The inverter G3 applies the inverted output to the gate of the PMOS transistor M4.
The operation of the current cell matrix type D-A converter is described below. When predetermined input digital code is applied to the X-decoder XD and the Y-decoder YD, current source cells in the cell matrix MX the number of which corresponds to the input digital code turn on to supply currents which in turn are added together to flow into the load resistor R.sub.L. Thus, the current cell matrix type D-A converter provides an analog output voltage corresponding to the input digital code.
The reason why the outputs I.sub.OUTB and I.sub.OUT from each current source cell SL are complementary to each other is to provide a constant amount of heat generated by the entire device independently of the input digital code.
The reference voltage generator circuit RG is a circuit for generating the reference voltage V.sub.BIAS required to operate the PMOS transistors M1 and M2 of each current source cell SL as a constant current source.
In the above described current cell matrix type D-A converter (also referred to simply as a D-A converter hereinafter), the reference voltage generator circuit RG is designed so that the reference voltage V.sub.BIAS generated by the reference voltage generator circuit RG during standby equals the voltage of the power supply V.sub.DD for reduction in power consumption during standby (when the system is suspended).
FIG. 13 shows the construction of the reference voltage generator circuit RG. As illustrated in FIG. 13, the reference voltage generator circuit RG comprises NMOS transistors M7, M8, M9, PMOS transistors M10, M11, M12, M13, an inverter G4, and a resistor R1.
The drains of the NMOS transistors M7 and M8 are connected to each other, and the sources of the NMOS transistors M7 and M8 are grounded. The PMOS transistor M10 has a drain connected through the resistor R1 to the drains of the NMOS transistors M7 and M8, and a source connected to the power supply V.sub.DD. The PMOS transistor M11 has a gate grounded, a source connected to the power supply V.sub.DD, and a drain connected to the source of the PMOS transistor M12. The PMOS transistor M12 has a drain connected to the drain of the NMOS transistor M9. The NMOS transistor M9 has a source grounded, and a gate connected to the gate of the NMOS transistor M8. The gate of the NMOS transistor M8 is connected to the drains of the NMOS transistor M7 and M8.
The PMOS transistor M13 has a source connected to the power supply V.sub.DD, and a drain connected to the gate of the PMOS transistor M12. The gate of the PMOS transistor M12 is connected to the draw thereof. The drain of the PMOS transistor M13 and the gate of the PMOS transistor M12 are connected to an output end VT of the reference voltage V.sub.BIAS.
A stop signal STOP which is one of the control signals provided from the exterior of the D-A converter is input to the gate of the PMOS transistor M10 and the gate of the NMOS transistor M7. An inverted stop signal STOPB obtained by inverting the stop signal STOP in the inverter G4 is input to the gate of the PMOS transistor M13.
The operation of the reference voltage generator circuit RG is described below. The stop signal STOP is a control signal for switching the D-A converter between an operating state and a standby state. In the operating state, the stop signal STOP is at a potential of low level (referred to hereinafter as "L"). This turns on the PMOS transistor M10 and turns off the NMOS transistor M7 and the PMOS transistor M13. Thus, the reference voltage generator circuit RG acts as a current mirror circuit to provide a predetermined operating voltage Vop as the reference voltage V.sub.BIAS.
In the standby state, the stop signal STOP is at a potential of high level (referred to hereinafter as "H"). This turns on the NMOS transistor M7 and the PMOS transistor M13 and turns off the PMOS transistor M10. Thus, the reference voltage V.sub.BIAS equals the voltage (V.sub.DD) of the power supply V.sub.DD. In this case, the PMOS transistors M1 and M2 of the current source cell SL which receives the reference voltage V.sub.BIAS turn off, and the PMOS transistor M9 of the reference voltage generator circuit RG also turns off. Therefore, there is no path of current flowing from the power supply V.sub.DD to the ground (GND) in the reference voltage generator circuit RG and the current source cell SL, resulting in a small amount of power consumption.
With the D-A converter in the operating state, the time required for the stop signal STOP to rise from "L" to "H" to place the D-A converter into a complete standby state (i.e., transition time) is determined by the time required to charge the gates of the PMOS transistors M1 and M2 in the current source cell SL. Hence, the transition time may be controlled by changing the gate width of the PMOS transistor M13.
With the D-A converter in the standby state, on the other hand, when the stop signal STOP falls from "H" to "L," electric charges stored at the gates of the PMOS transistors M1 and M2 in the current source cell SL are discharged through the NMOS transistor M9 of the reference voltage generator circuit RG, thereby to decrease the reference voltage V.sub.BIAS from the power supply voltage V.sub.DD to the operating voltage level Vop. This transition time in the standby state is determined by the size of the NMOS transistor M9.
The size of the NMOS transistor M9 is set in consideration for the occupied area thereof in the reference voltage generator circuit RG and the power consumption during operation, for example, so that the NMOS transistor M9 acts as a source of current which is one-sixteenth the output I.sub.OUT from the current source cell SL when all bits of the input digital code applied to the X-decoder XD and the Y-decoder YD of the D-A converter are "1."
The transition time is not dramatically shortened even if the gate width of the NMOS transistor M9 is doubled. Therefore, the reference voltage generator circuit RG shown in FIG. 13 is not capable of arbitrarily controlling the standby-state to operating-state transition time.
FIG. 3A shows the stop signal STOP when supplied, and FIG. 3B shows a circuit simulation result of the D-A converter when the reference voltage generator circuit RG is used. Specifically, FIG. 3B shows plots of an output voltage Vout from the current source cell SL when all bits of the input digital code applied to the X-decoder XD and the Y-decoder YD are "1" and the stop signal STOP rises from "L" (i.e. 0 V) to "H" (i.e. full scale) at the time of 100 ns (nsec) and falls from "H" to "L" at the time of 500 ns as shown in FIG. 3A. The horizontal axis of FIGS. 3A and 3B represents elapsed time (sec) and the vertical axis represents voltage (V).
It is understood from FIG. 3B that the use of the background art reference voltage generator circuit RG results in the transition time of not less than 500 ns required for the stop signal STOP to fall to cause the D-A converter to make the standby-state to operating-state transition (defined herein as the time required for the output voltage Vout which is 0 V at the time of 500 ns to reach the operating-state value of the output voltage Vout.+-.1 LSB). This transition time is a dozen times greater than the clock cycle of the D-A converter, and the D-A converter does not perform its normal operation during the transition time.